1. Field of the Invention
The present invention relates to semiconductor memories and in particular a three level concurrent word line bias condition for NOR type flash memory arrays.
2. Description of the Related Art
In today""s flash EEPROM technology, a plurality of one-transistor EEPROM cells has been configured into either NAND-type or NOR-type memory arrays. For the NAND type cell array, the sources and drains of the flash cells are connected in series to save die size for the reason of cost reduction. In contrast, for NOR-type cell array, the drains and sources of the cells are connected in parallel to bit lines and source lines, respectively, to achieve high read speed at sacrifice of the increase in die size. It is well known that the NAND-type cell array suffers no over-erase problem due to its unique array structure allowing no leakage path during read. For a one transistor (non-split gate) NOR-type cell array, the over erase problem may or may not occur, and the over erase problem is subject to the choice of erase and program methods. Conventionally, a program operation is performed on the basis of bit-by-bit method but erase is performed collectively on all cells in a block. In both the NOR-type or NAND-type flash memory, the entire flash chip is divided into several blocks, and typically, the size of each flash block ranges from 64 Kbits to 512 Kbits. An erase operation is performed prior to program operation, and in a NAND-type flash memory, the erase is performed on a block (sector) basis and program is performed on a page basis.
A page is usually defined as a word line and a block is defined as many word lines which share common bit lines within the same divided block. Although several methods of erase and program operations have been proposed, in the current NAND type flash memory, the definition of erase and program operations is unified. The erase operation is to decrease the Vt (threshold voltage) of the cells that are physically connected to the same erased word line or the word lines in the same block. In contrast, the program operation is to increase the Vt of cells of selected erased word line or word lines in the selected block. The non-selected cells in the non-selected word lines in the selected block or the non-selected blocks remain undisturbed.
The following U.S. patents of prior art are directed toward the detailed description of NAND type flash EPROM""s.
A) U.S. Pat. No. 6,038,170 (Shiba) is directed toward a nonvolatile memory of a hierarchical bit line structure having hierarchical bit lines which includes a plurality of sub-bit lines.
B) U.S. Pat. No. 5,464,998 (Hayakawa et al.) is directed toward a non-volatile semiconductor memory device including NAND type memory cells arranged in a matrix pattern over a semiconductor substrate.
Up to the present, the definition of erase and program operations for a one-transistor cell, NOR-type flash memory is inconsistent. Erase could be defined to increase cell""s Vt and program to decrease cell""s Vt, or vise versa depending on the preferred flash technology and its design techniques. The following is a summary of erase and program operations for state, of the art one-transistor (non-split-gate) NOR-type flash EEPROM technologies.
I) FN (Fowler-Nordheim) Block erase, CHE (channel hot electron) program, one-transistor cell, NOR-type flash, EEPROM technology. The typical example is an ETOX flash cell. In this prior art, programming is performed on bit-by-bit basis to increase the Vt of the cells by using the CHE method while erase is performed on block basis to decrease the Vt of the cells by using FN-tunneling method. The CHE program consumes more than 300 uA per bit, therefore only a few bits can be programmed at a time by an on-chip charge pump having an economic semiconductor area. Unlike CHE, FN-tunneling erase requires only 10 nA per flash cell so that a big block size of 512 Kb can be erased simultaneously. For a Vdd voltage of 3V or lower, about 4 bits of ETOX cells are programmed in state-of-the art design. In a CHE operation, hot electrons are injected into cell""s floating gate with an increase in Vt. In contrast, in the FN tunneling operation, the electrons are extracted out of the floating gate with a decrease in Vt. The erase operation is called an edge erase operation which is done at edge of the thin tunnel oxide between the floating gate and the source junction. In the ETOX flash cell, the source junction of N+ is used for an erase operation only which is made to be much deeper than the drain node. The source junction of N+ is surrounded with lightly doped N-implant to reduce the peak electrical field generated during erase operation at the tunneling edge. The drain junction is formed with a shallow N+, with a P+ implanted underneath to enhance the electrical field for CHE program. The ETOX cell is made non-symmetrical with respect to source and drain junctions of the cell in terms of cell structure and operating conditions; therefore, it is very difficult to shrink the cell using technology below 0.18 um for Ultra-high integrated memory.
The key operating conditions for the ETOX technology with a cell made on a P-substrate are as follows:
The drawbacks of the ETOX flash cell are: a) a low cell scalability resulting from an asymmetrical cell structure with a deep source junction; b) a high program current caused by the CHE program scheme; c) a high erase current resulting from using an edge-FN scheme with large substrate leakage current; d) severe over erase potential caused by decreasing the Vt of cells during erase operation; e) a channel punch through problem in short channel lengths due to the edge erase.
The following U.S. patents of prior art are directed toward the detailed description of ETOX flash cell operations:
A) U.S. Pat. No. 5,712,815 (Colin et al.) is directed toward an improved programming structure for performing a program operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided.
B) U.S. Pat. No. 5,790,456 (Haddad) is directed toward an improved method for performing channel hot-carrier programming in an array of multiple bits-per-cell Flash EEPROM memory cells in a NOR memory architecture so as to eliminate program disturb during a programming operation.
C) U.S. Pat. No. 6,011,715 (Pasotti et al.) is directed toward a programming method for a nonvolatile memory which includes several steps that are repeated until a final threshold value is obtained.
D) U.S. Pat. No. 5,825,689 (Wakita) is directed toward a nonvolatile semiconductor memory device including a memory cell array in which the threshold voltage of a transistor constituting the memory cell is at ground potential or less, and the source voltage condition is changed by a source potential setting circuit in accordance with a detection result from a data detecting circuit.
II) AND one-transistor cell, NOR-type flash EEPROM technology. Unlike ETOX technology, in the AND one transistor prior art the program is performed on bit-by-bit basis to decrease the Vt of cells while erase is performed on block basis to increase the Vt of cells. Both erase and program operations use the FN-tunneling method which consumes only about 10 nA per bit; therefore, a large number of flash cells within a large block can be erased simultaneously by an on-chip charge pump which utilizes a small area on the chip. For a single low power supply, Vdd, is at 3V or below, and as many as 16 Kb of cells of the AND technology in a block can be erased. In the AND prior art, the erase operation is carried out by FN block channel erase, and the program operation is carried out by page FN edge program. The edge program is at the drain edge formed by a buried N+ bit line . The electrons are injected into cell""s floating gate by block channel erase operation with an increase in the Vt of the erased cells. In contrast, electrons are extracted out of a floating gate by a page edge program operation where the Vt of the programmed cells decreases. In this AND flash cell, the N+ drain junction is used for program operation only and is made to be much deeper than the source node. The N+ drain junction is surrounded with a lightly-doped N-implant to reduce the peak electrical field that is generated during the drain-edge-program operation. The source junction is formed with a shallow N+ having a P+ implant underneath to prevent voltage punch-through in a short channel region during an edge program operation. The AND cell like the ETOX cell is made non-symmetrical with respect to the source and drain junctions in terms of cell structure and operating conditions. Therefore, it is very difficult to shrink the AND cell below 0.18 um technology for an ultra-high integrated memory.
The key operating conditions for this technology with cell made on P-substrate are summarized as follows.
The drawbacks of the AND flash cell are: a) low cell scalability caused by asymmetrical cell structure with a deeper drain than source junction; b) high program current resulting from the edge-FN program scheme with large substrate leakage current; c) severe channel punch-through problem in shorter channel length resulting from the edge program.
The detailed description of AND flash cell operations can be referred to the following U.S. patents of prior art:
A) U.S. Pat. No. 6,072,722 (Hirano) is directed toward programming and erasing a non-volatile semiconductor storage device.
B) U.S. Pat. No. 6,101,123 (Kato et al.) is directed toward programming and erasing verification of a non-volatile semiconductor memory.
C) U.S. Pat. No. 6,009,016 (Ishii et al.) is directed toward a nonvolatile semiconductor memory which recovers variation in the threshold of a memory cell due to disturbance related to a word line.
D) U.S. Pat. No. 5,982,668 (Ishii et al.) is directed toward a nonvolatile semiconductor memory which recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation.
E) U.S. Pat. No. 5,959,882 (Yoshida et al.) is directed toward a nonvolatile semiconductor memory device with a plurality of threshold voltages set so as to store multi-valued information in one memory cell entitled.
F) U.S. Pat. No. 5,892,713 (Jyouno et al.) is directed toward a configuration that provides a nonvolatile semiconductor memory device which allows high-speed block reading.
G) U.S. Pat. No. 5,757,699 (Takeshima et al.) is directed toward the programming of a selected memory cell which is repeated until the programmed threshold voltage is not greater than a predetermined threshold voltage.
III) FN-erase, FN-program, Metal-bit line, One-transistor, NOR-type Flash EEPROM. Like AND flash technology, in this prior art, the program operation is performed on a bit-by-bit basis to decrease the Vt of cells while erase is performed on a block basis to increase the Vt of cells. Both erase and program operations use the FN-tunneling method, which consumes only about 10 nA per bit without taking the greater substrate current into account. Therefore a large number of flash cells within a big block can be erased at one time by an on-chip charge pump having economic area. For a single low power supply, Vdd, of 3V or below, a larger number of flash cells in a block can be programmed and erased simultaneously. In the prior art, the erase operation is carried out by FN channel-erase, and the program operation is carried out by FN edge-program. The edge-program is at the drain edge but the cell structure is formed by a non-buried N+ bit line and a source line. The bit line is a vertical metal line which connects all drains of the cells in the same block for high read speed. The source lines are tied together by an N+ active line, which runs in parallel to the word lines. Each source line is shared by one pair of word lines as in the ETOX flash cell array. As disclosed in the prior art, the electrons are removed from the floating gate of the cells by drain edge FN programming in which the Vt is decrease. Conversely, the electrons are injected into the floating gate by channel erasing where Vt is increased. The N+ drain junction is used for the FN program operation and is made to be much deeper than source node, and is surrounded with a lightly doped N-implant to reduce the peak electrical field generated during drain edge program operation. The source junction is formed with shallow N+ with a P+ implant underneath the source to prevent voltage punch-through in a short channel region during edge-program operation. The flash cell of prior art is made asymmetrical with respect to source and drain junctions in terms of cell structure and operating conditions; therefore, it is difficult to further shrink the memory cell for Ultra-high density memory below 0.18 um technology.
The key operating conditions for the NOR type flash technology with a cell formed on a P-substrate are as follows:
The drawbacks of the NOR type flash cell are: a) Low cell scalability as a result of an asymmetrical cell structure with the drain junction deeper than the source junction; b) high program current caused by the edge-FN program scheme with a large substrate leakage current.; c) severe channel punch-through problem in shorter channel lengths caused by the edge program. The detailed description of the NOR type flash technology can be referred to in U.S. Pat. No. 5,708,600 (Hakozaki et al.) which is directed toward a method for writing a multiple value into a nonvolatile memory capable of multiple value data being written into a floating gate type memory cell.
An object of the present invention is to provide a three level concurrent word line bias condition and method using CHE program and FN block erase for a semiconductor nonvolatile device and in particular, for an ETOX one transistor cell, and a NOR-type EEPROM memory array formed on P-substrate.
Another object of the present invention is to provide a three level word line bias condition and methods using FN schemes for both program and erase operations for a one transistor cell, NOR type AND EEPROM memory array formed on P-substrate.
Another objective of the present invention is to provide a three level word line bias condition and methods using CHE program and FN block-erase for a semiconductor nonvolatile device, in particular an ETOX one transistor cell, NOR type EEPROM memory array formed on p-well which is within a deep N-well on top of p-substrate.
Still another objective of the present invention is to provide a new operation method that employs the three level word line bias condition to perform the bit-by-bit verify and correction for achieving both tight xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d for distributions of Vt.